1. Field of the Invention
The present invention relates to a semiconductor device having a MOS transistor formed on a SOI substrate, and more particularly to an input-output protecting function thereof.
2. Description of the Background Art
In the case where a MOS device is formed on a bulk silicon substrate, a surge can be discharged into the substrate through a PN junction. In a SOI (Silicon-on-insulator) device in which the MOS device is formed on a SOI layer provided on a buried insulation layer, a path for transferring the surge does not structurally exist on the substrate because the buried insulation layer is formed. In particular, a longitudinal discharge path does not exist in a thin film SOI structure in which source and drain regions of a MOS transistor reach a buried oxide film. Consequently, it is structurally necessary to perform a transverse discharge. For this reason, the discharge is transversely performed into a power line and a grounding line through the MOS transistor and a diode.
FIG. 31 is a circuit diagram showing a structure of an input-output protecting circuit having a SOI structure according to the prior art. As shown in FIG. 31, one of ends of a resistor 36 (hereinafter referred to as a "protecting resistor") for limiting a rush current is first connected to a signal terminal 30 to delay propagation of a surge voltage to an inside through the signal terminal 30, thereby preventing an excessive current from flowing. Then, a PMOS transistor Q31 and an NMOS transistor Q32 are provided in series as discharge elements for transferring electric charges between a power supply (node) 32 and a ground level (node) 33. The PMOS transistor Q31 and the NMOS transistor Q32 have gates connected to the power supply 32 and the ground level 33, and drains connected to the other end of the protecting resistor 36 in common, respectively. Accordingly, the PMOS transistor Q31 and the NMOS transistor Q32 are usually brought into an OFF state.
In the case where the surge voltage is applied to the signal terminal 30, the electric charges are quickly discharged into the power supply 32 or the ground level 33 by avalanche breakdown of each of the MOS transistors Q31 and Q32 to protect an internal element 31. Furthermore, the other end of the protecting resistor 36 is connected to one of ends of an internal resistor 37, and the internal element 31 is connected to the other end of the internal resistor 37. Consequently, the surge voltage is propagated to the internal element 31 with difficulty.
FIG. 32 shows an input-output protecting circuit formed by using diodes 38 and 39 as discharge elements in the same manner. As shown in FIG. 32, one of ends of a protecting resistor 36 is first connected to a signal terminal 30 to delay propagation of a surge voltage to an inside through the signal terminal 30, thereby preventing an excessive current from flowing. Then, the diodes 38 and 39 are provided in series as discharge elements for transferring electric charges between a power supply 32 and a ground level 33. A cathode of the diode 38 is connected to the power supply 32, and an anode of the diode 39 is connected to the ground level 33. Accordingly, the diodes 38 and 39 are connected in reverse directions between the power supply 32 and the ground level 33.
If the surge voltage is applied to the signal terminal 30, the electric charges are quickly discharged into the power supply 32 or the ground level 33 by backward avalanche breakdown of the diodes 38 and 39 or a forward current, thereby protecting an internal element 31. Furthermore, an internal resistor 37 is inserted between the protecting resistor 36 and the internal element 31 to propagate the surge voltage to the internal element 31 with difficulty.
FIG. 33 shows an inverter circuit acting as one of typical internal circuits. As shown in FIG. 33, a PMOS transistor Q33 and an NMOS transistor Q34 are connected in series between a power supply 32 and a ground level 33. The PMOS transistor Q33 and the NMOS transistor Q34 have gates connected to an input signal terminal 82 in common, and drains connected to an output signal terminal 83 in common.
In the case where the input-output protecting circuits having the structures shown in FIGS. 31 and 32 are connected to the input signal terminal 82 (an input section of the internal circuit) for the internal circuit shown in FIG. 33, they function as input protecting circuits. In the case where the same input-output protecting circuits are connected to the output signal terminal 83 (an output section of the internal circuit), they function as output protecting circuits. The function and operation of the protecting circuit are the same in the input and output sections. Therefore, the protecting circuit will be hereinafter referred to as an "input-output protecting circuit". If the protecting circuit is used as the output protecting circuit, no resistor is often added thereto.
FIG. 34 is a plan view showing a planar structure of the MOS input-output protecting circuit shown in FIG. 31, and FIG. 35 is a sectional view taken along the line A--A shown in FIG. 34. As shown in FIGS. 34 and 35, a thin silicon film 3 acting as a SOI layer is provided on a silicon substrate 1 with a buried oxide film 2 acting as an insulation layer interposed therebetween. The thin silicon film 3 is divided into two islands 18A and 18B by an interlayer dielectric film 11. Channel formation regions 6 and 6d into which an impurity having a concentration of about 10.sup.17 /cm.sup.3 (p-type in NMOS and n-type in PMOS) is implanted are provided, drain and source regions 7 and 8 into which an impurity having a concentration of about 10.sup.20 /cm.sup.3 (n-type in NMOS and p-type in PMOS) is implanted are provided with the channel formation region 6 interposed therebetween, and drain and source regions 7d and 8d into which an impurity having a concentration of about 10.sup.20 /cm.sup.3 is implanted are provided with the channel formation region 6d interposed therebetween. Furthermore, gate electrodes 5 and 5d are formed on the channel formation regions 6 and 6d and a part of each of the drain regions 7 and 7d and the source regions 8 and 8d in the thin silicon film 3 with gate oxide films 4 and 4d interposed therebetween, respectively. Accordingly, the NMOS transistor Q32 is formed by the gate oxide film 4, the gate electrode 5, the channel formation region 6, the drain region 7 and the source region 8 in the island 18A, and the PMOS transistor Q31 is formed by the gate oxide film 4d, the gate electrode 5d, the channel formation region 6d, the drain region 7d and the source region 8d in the island 18B.
Furthermore, the interlayer dielectric film 11 divides the thin silicon film 3 into the islands 18A and 18B and is formed over the whole surface of the thin silicon film 3. Contact holes 12A to 12D are provided on the interlayer dielectric film 11 in a part of each of the drain regions 7 and 7d and the source regions 8 and 8d. An aluminum wiring 14 is electrically connected to the drain regions 7 and 7d through the contact holes 12A and 12B, an aluminum wiring 13 is electrically connected to the source region 8 through the contact hole 12C, and an aluminum wiring 15 is electrically connected to the source region 8d through the contact hole 12D. The aluminum wiring 13 is connected to a ground level 33, the aluminum wiring 14 is connected to an input section 30d, and the aluminum wiring 15 is connected to a power supply 32. The input section 30d means a portion to be connected to the other end of the protecting resistor 36 as shown in FIG. 32. In FIG. 34, the interlayer dielectric film 11 is omitted.
As shown in FIG. 34, the protecting resistor 36 formed of a gate electrode material and a thin silicon film is provided between the signal terminal 30 and the PMOS transistor Q31 and NMOS transistor Q32 which act as discharge elements, and the internal resistor 37 formed of the gate electrode material and the thin silicon film is provided between the discharge elements Q31 and Q32 and the internal element 31. The protecting resistor 36 is usually resistant to a rush current flowing into the discharge elements Q31 and Q32. Therefore, a width of the protecting resistor 36 is made greater than that of the internal resistor 37, thus reducing a current density.
The gate electrode 5d of the PMOS transistor Q31 is connected to the power supply 32 by a gate potential fixing wiring 40, and the gate electrode 5 of the NMOS transistor Q32 is connected to the ground level 33 by a gate potential fixing wiring 41. The PMOS transistor Q31 and the NMOS transistor Q32 are set into an OFF state, respectively.
The next operation will be described below with reference to FIGS. 31, 34 and 35. A surge generated by static electricity is sent through the signal terminal 30 and is first delayed by the protecting resistor 36 to prevent a great rush current from flowing into the discharge elements Q31 and Q32. The surge propagated through the protecting resistor 36 is then discharged quickly into the power supply 32 or the ground level 33 through the discharge elements Q31 and Q32. The internal resistor 37 does not function to cause the surge to flow in a direction of the internal element but in a direction of the discharge element. The surge propagated through the protecting resistor 36 is applied to a discharge element section. If a positive surge voltage is applied, a junction breaks down between the drain region 7 and the channel formation region 6 of the NMOS transistor Q32 to emit the surge to the ground level 33. At the same time, the PMOS transistor Q31 is forward biased and the surge is emitted to the power supply 32 as well. If a negative surge voltage is applied, a junction breaks down between the drain region 7d and the channel formation region 6d of the PMOS transistor Q31 to emit the surge to the power supply 32 and the NMOS transistor Q32 is forward biased to emit the surge. During normal operation, the PMOS transistor Q31 and the NMOS transistor Q32 are set in the OFF state. Therefore, an normal operation signal applied to the signal terminal 30 is propagated to the internal element 31 through the protecting resistor 36 and the internal resistor 37.
FIG. 36 is a sectional view showing a sectional structure of the diode type input-output protecting circuit shown in FIG. 32. As shown in FIG. 36, a thin silicon film 3 is provided on a silicon substrate 1 with a buried oxide film 2 acting as an insulation layer interposed therebetween. The thin silicon film 3 is divided into two islands 19A and 19B by an interlayer dielectric film 11. An anode region 9B into which a p-type impurity having a concentration of about 10.sup.17 /cm.sup.3 is implanted, and a cathode region 10B into which an n-type impurity having a concentration of about 10.sup.17 /cm.sup.3 is implanted are provided, respectively. An anode region 9A and a cathode region 10A are provided with the anode region 9B interposed therebetween. An anode region 9C and a cathode region 10C are provided with the cathode region 10B interposed therebetween. A p-type impurity having a concentration of about 10.sup.20 /cm.sup.3 is implanted into the anode regions 9A and 9C, and an n-type impurity having a concentration of about 10.sup.20 /cm.sup.3 is implanted into the cathode regions 10A and 10C.
Furthermore, an electrode 5 is formed on the anode region 9B and a part of the anode region 9A and the cathode region 10A in the thin silicon film 3 with an oxide film 4 interposed therebetween, and an electrode 5d is formed on the cathode region 10B and a part of the anode region 9C and the cathode region 10C in the thin silicon film 3 with an oxide film 4d interposed therebetween. A diode 39 is formed by the anode regions 9A and 9B and the cathode region 10A. A diode 38 is formed by the anode region 9C and the cathode regions 10B and 10C.
A structure of a diode section is the same as that shown in FIG. 35. The anode regions 9B and 9A and the cathode region 10A are replaced with the channel formation region 6, the source region 8 and the drain region 7, respectively. The cathode region 10B, the anode region 9C and the cathode region 10C are replaced with the channel formation region 6d, the drain region 7d and the source region 8d, respectively. While the electrodes 5 and 5d are used as masks during formation of the anode regions 9A and 9C and the cathode regions 10A and 10C, they do not function as components of the element.
The next operation of the input-output protecting circuit shown in FIGS. 32 and 36 is the same as that of the input-output protecting circuit shown in FIGS. 31 and 35 except that emission is performed with breakdown of a junction of the anode region 9B and the cathode region 10A of the diode 39 and breakdown of a junction of the anode region 9C and the cathode region 10B of the diode 38.
In the SOI structure, a thermal conductivity is poor due to existence of the buried oxide film 2, a temperature rise is great even if the same power as that of a bulk element formed on a bulk substrate is put into the discharge element (the temperature rise being about three times as much as that in the bulk substrate), and secondary breakdown (thermal runaway) is caused so that destruction is easily caused. Furthermore, a current flows ununiformly and concentrates on a part of the elements. Consequently, a rapid temperature rise occurs in the element on which the current concentrates. Thus, only the same element causes the secondary breakdown. As a result, an ESD (Electrostatic discharge) resistance of a whole device is deteriorated.
With the SOI structure, furthermore, quality of the thin silicon film 3 is not so good as that of the bulk substrate. Therefore, quality of the gate oxide film 4 formed on the thin silicon film 3 is easily deteriorated so that the ESD resistance is degraded. The deterioration in the quality of the gate oxide film 4 is particularly remarkable in an active region boundary portion (an isolating end) of the thin silicon film 3 having a height difference from the insulation layer 2.